The present invention relates generally to semiconductor packaging and, more particularly, to a hybrid system-in-package (SiP) with flip-chip and wire-bonded chip on a fan-out redistribution layer (RDL) carrier. An exemplary method for fabricating such hybrid system-in-package is also disclosed.
As known in the art, there are a variety of chip package techniques such as ball grid array (BGA), wire bonding, flip-chip, etc. for mounting a die on a substrate via the bonding points on both the die and the substrate. In order to ensure miniaturization and multi-functionality of electronic products or communication devices, semiconductor packages are required to be of small in size, multi-pin connection, high speed, and high functionality.
Wire-bonding System-in-Package (wBSiP) technology is widely used because it can increase the capacity of the semiconductor package. wBSiP includes a plurality of chips, which are stacked and may be connected to each other by way of wire bonding. However, the conventional wBSiP encounters several problems, for example, the thickness of the package, ability to support fine pitch pad, and low-resistance/inductance IP.
Increased Input-Output (I/O) pin count combined with increased demands for high performance ICs has led to the development of Flip-Chip Packages. Flip-chip technique uses bumps on bonding pads on chip to interconnect directly to the package medium. The chip is bonded face down to the package medium through the shortest path. The technique can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units. The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package.
FIG. 1 is a schematic, cross-sectional diagram illustrating a conventional flip-chip chip scale package (FCCSP). As shown in FIG. 1, the FCCSP 100 comprises a die 101 mounted face-down on a top surface of the carrier 120 and is connected to the carrier 120 through solder bumps 102. A plurality of solder balls 122 are provided on a bottom surface of the carrier 120 for the connection with a circuit board. This package construction typically utilizes eutectic tin/lead flip-chip interconnect technique, in either area array or peripheral bump layout, replacing standard wire-bond interconnect. The elimination of wire-bond loops allows for a low inductance connection to the die, while the increased routing density enables optimized electrical paths for critical high frequency signal lines.
FIG. 2 is a schematic, cross-sectional diagram illustrating a conventional flip-chip ball grid array (FCBGA) package. As shown in FIG. 2, the FCBGA package 200 comprises a die 201 mounted face-down on a top surface of a chip carrier substrate 220 and is connected to the chip carrier substrate 220 through the solder bumps 202. An underfill 203 fills the gap between the die 201 and the top surface of the chip carrier substrate 220. The chip carrier substrate 220 may comprise multi-layer traces, and different layers of traces are interconnected together through blind via 222 or buried via 224. For example, the blind via 222 may be drilled by laser for achieving a higher density. A plurality of solder balls 226 are provided on a bottom surface of the chip carrier substrate 220. The FCBGA package 200 allows for the design of advanced packaging solutions that are ideal for current and future high-speed networking and digital TV systems. For example, to maintain signal integrity, this package features low inductance, low dielectric loss and impedance matching.
However, the conventional flip-chip technique is facing the challenge of bump pitch limitation on the substrate. Besides, a high-performance FCBGA package is costly due to the expensive chip carrier substrate that typically comprises 1+2+1 or more-layer build up. The bottleneck of the flip-chip roadmap is the bump pitch of the substrate since the development and shrinkage of the bump pitch is much slower than the die shrinking and the increase of the pin count. Even the die shrinking will exceed the shrinkage of bump pitch resolution on substrate carrier in the future. To conquer the issue of such technology gap, silicon interposer and TSV (Through Silicon Via) technology, and fine pitch bump technology are preferred solutions. However, the above-mentioned technologies are very expensive and involve complex fabrication processes.
Therefore, there is a strong need in this industry to provide an improved flip-chip package or a system-in-package (SiP) that has improved routing flexibility with fine pitch, and is cost-effective, and can overcome the bump pitch limitation on the substrate. Further, it is desirable to provide a semiconductor package with improved routing flexibility on the package substrate.